In recent years, there has been remarkable advancement of high-speed semiconductor devices, and as semiconductor devices become faster, an output circuit having a differential construction as shown in FIG. 4, for example, is currently used in memory devices. In the output circuit shown in FIG. 4, Nch transistors N1 and N2 form a differential pair, and the drain of an Nch transistor N3 for adjusting the output amplitude is connected to the sources of the Nch transistors N1 and N2. In the Nch transistor N3 whose source is grounded, the amplitude of the output signal is adjusted by applying a signal CC as a specified voltage to the gate. Input/output terminals DQ, DQN are connected to the drains of the Nch transistors N1, N2, respectively, and one of the ends of the termination resistors R1, R2 is also respectively connected as a load. The other ends of the termination resistors R1, R2 are respectively connected to the drains of Pch transistors P1, P2 for adjusting the terminating resistance. The drains of the Pch transistors P1, P2 are connected to a power supply, and the gates are grounded. Here, the Pch transistors P1, P2 are in the ON state. During data output, read-data signals RD, /RD (the symbol ‘/’ means the signal is inverted) that are input to the gates of the Nch transistors N1 and N2 as differential signals drive the input/output terminals DQ and DQN. In an output circuit with this kind of construction, in order to increase the operating speed during normal operation, the output amplitude of the input/output terminals DQ, DQN is about several hundred mV.